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as4c4m16s revision history as4c4m16s - 54pin 400 mil plastic tsop ii package revision details date rev 1.0 preliminary datasheet february 201 1 rev 2.0 removed 6ta n C C automotive temp page 1 and page 52 (see separate datasheet for this option) may 2014 added 6t cn C 166mhz clock C commercial temp page 1 and page 52 may 2014 ad ded in temperature range to page 1 * operating temperature range - commercial (0 ~ 70c) - industrial ( - 40 ~ 85c) may 2014 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change p roducts or specification without notice.
as4c4m16s - 6/7 tck3 clock c y cle ti m e( m in.) 6/7 ns tac3 access ti m e from clk( m a x .) 5.4/5.4ns tras row active time(min.) 42/49 ns trc row cycle time(min.) 60/63 ns part number frequenc y package as4c4m16s - 6t c n 166mhz tsop ii as4c4m16s - 6ti n 166 mhz tsop ii as4c4m16s - 7tcn 143mhz tsop ii february 20 11 as 4 c 4m16s 64mb / 4m x 16 bit synchronous dram (sdram) alliance memory rev2.0 may 2014 features ? fast access time from clock: 5.4/5.4 ns ? fast clock rate: 166/143 mhz ? fully synchronous operation ? internal pipelined architecture ? 1m word x 16-bit x 4-bank ? programmable mode registers - cas latency: 2, or 3 - burst length: 1, 2, 4, 8, or full page - burst type: interleaved or linear burst - burst stop function ? auto refresh and self refresh ? 4096 refresh cycles/64ms ? cke power down mode ? single +3.3v 0.3v power supply ? interface: lvttl ? 54 -pin 400 mil plastic tsop ii package - pb free and halogen free table1. key specifications table 2. ordering information t: indicates tsopii package, n: indicates pb and halogen free for tsopii package figure 1.pin assignment (top view) overview the as4c4m16s sdram is a high-speed cmos synchronous dram containing 64 mbits. it is internally configured as 4 banks of 1m word x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). read and write accesses to the sdram are burst oriented; accesses st art at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bankactivate command which is then followed by a read or write command. the as4c4m16s provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. an auto precharge function ma y be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable mode s to maximize its performance. these devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance pc applications. vdd dq0 vddq dq1 dq2 vss q dq3 dq4 vddq dq5 dq6 vss q dq7 vdd ldqm we# cas# ras # cs# ba0 ba1 a1 0 / ap a0 a1 a2 a3 vdd 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 vss dq 15 vssq dq14 dq 13 vddq dq 12 dq 11 vssq dq 10 dq9 vddq d q8 vss nc/rf u udqm cl k cke nc a11 a9 a8 a7 a6 a5 a4 vss * operating temperature range - commercial (0 ~ 70c) - industrial (-40 ~ 85c) . 1 rev2.0 may 2014
~ row decoder r ow d ecoder r ow d ecoder r ow decoder ~ february 20 11 as 4 c 4m16s figure 2. block diagram cke buffer 1 m x 16 cell arr a y (bank # a) c o l u m n d ec o d e r cs# r a s# c a s# we# command decoder cont r o l signal gene r ato r dq buffer dq0 dq15 l d qm , ud qm a 1 0/ a p c o lu mn co u n ter m o de register 1 m x 16 cell a rray ( b an k #b) column de c o d e r a0 a9 a11 b a 0 b a 1 address buffer refresh counter 2 rev2.0 may 2014
s y mbol t y pe description clk input clock: clk is driven by the system clock. al l sdram input signals are sample on the po sitive edge of clk. clk also in crements the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivates (low) the clk signal. if cke goes low synchronousl y with clock (set - up and hold time same as other inputs), the internal clock is suspended from the next clock c y cle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the c lock controls the entry to the power down and self refresh modes. cke is s y nchronous except after the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the in put buffers, including clk, are disable d during power down and self refresh modes, providing low standby power. ba0,ba1 input bank acti v ate: ba0, ba1 input select the bank for operation. ba1 ba0 sele c t bank 0 0 bank #a 0 1 bank #b 1 0 bank #c 1 1 bank #d a0 - a11 input address in puts: a0 - a11 are sampled during the bankactivate command(row address a0 - a11) and read/write command (column address a0 - a7 with a10 defining auto precharge) to select one location out of the 1m available in the respective bank. during a precharge command, a 10 is sampled to determine if all banks are to be precharged (a10 = high). the address inputs also provide the op - code during a mode register set command. cs# input chip select: cs# enables (sampled low) and di sables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjun ction with the cas# and we# signals and is latched at the positive edges of clk. when ras# and cs# are asserted "low" and cas# is asserted "high," either the bankactivate command or t he precharge command is selected by the we# signal. when the we# is asse rted "h igh," the bankactivate command is selected and the bank designated by ba is t u rned on to the active state. when the we# is assert ed "low," the precharge command is selected and the bank designated by ba is switched to the idle state after the pr echarge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when ras# is held "high" and cs# is asserted "low," the column ac cess is s tarted by asserting cas# "low." then, the read or write command is selected by asserting we# "low" or "high." we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at th e positive edges of clk. the we# input is used to select the bank activate or precharge command and read or write command. february 20 1 1 as 4 c 4m16s pin descriptions table 3. pin details of as4c4m16s 3 rev2.0 may 2014
february 20 11 as 4 c 4m16s ldqm, udqm input data input/output mask: controls output buffers in read mo de and masks input data in write mode. dq0 - dq15 input / output data i/o: the dq0 - 15 input and output data are synchronized with the positive edges of clk. the i/os are maskable during reads and writes. nc/rfu - no connect: these pins should be left un connected. v ddq supply dq po w er: provide isolated power to dqs for improved noise immunity. ( 3.3 v 0.3v ) v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. ( 0 v ) v dd supply po w er suppl y : +3.3v 0.3v v ss supply gro und 4 rev2.0 may 2014
february 20 11 as 4 c 4m16s operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 4 shows the truth table for the operation comman ds. table 4. truth table (note (1), (2)) co mm and state cke n - 1 cke n dqm b a 0,1 a 10 a 0 - 9,11 cs# ras# cas# we# ban k a c tivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write a c tiv e (3) h x v v l column address (a0 ~ a7) l h l l write and autoprecharge activ e (3) h x v v h l h l l read activ e (3) h x v v l column address (a0 ~ a7) l h l h read and autoprecharge activ e (3) h x v v h l h l h mode register set idle h x x op code l l l l no - o peration any h x x x x x l h h h bur s t stop a c tive (4) h x x x x x l h h l devi c e de s ele c t any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefre s h exit idle (selfrefresh) l h x x x x h x x x l h h h clock suspend mode entry active h l x x x x h x x x l v v v power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode exit active l h x x x x x x x x power down mode exit any (po w erdo w n) l h x x x x h x x x l h h h data write/output enable active h x l x x x x x x x data ma sk / output di s able a c tive h x h x x x x x x x note: 1. v=valid, x=don't care l=low level h=high level 2. cke n signal is input level when commands are provided. cke n - 1 signal is input level one clock cyc l e before the commands are provided. 3. these are states of bank designated by ba signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this co mmand is asserted in the bu r st cycle, device state is clock suspend mode. 5 rev2.0 may 2014
february 20 11 as 4 c 4m16s commands 1 bankactivate (ras# = "l", cas# = "h", we# = " h ", bas = bank, a0 - a11 = row address) the bank activate command activates th e idle bank designated by the ba0, 1 signal. by latching the row address on a0 to a11 at the time of this command, the selected row access is initiated. the read or write operation in the same bank can occur after a time delay of t rcd (mi n.) from the time of bank activation. a subsequent bankactivate command to a different row in the same bank can only be issued after the previous active row has been precharged ( refer to the following figure). the minimum time interval between successive b ank activate comm an ds to the same bank is defined by t rc (min.). the sdram has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restri cts the back - to - back activation of the two banks. t rrd (min.) specifies the minimum time required between activating different banks. after this command is used, the write command and the block write command perform the no mask write operation. clk t0 t1 t2 t3 tn+3 tn+4 t n +5 tn+6 a d dress bank a row add r . ba n k a col a d d r . bank b row add r . bank a row a ddr. ra s # - c as# de l a y( t r c d ) r a s# - ras# d elay time ( t r r d ) comm a nd ba n k a a c tivate nop nop r/w a w i t h autopr e ch a r g e ba n k b a c tivate nop nop bank a a c tivate r a s# - cycle t i me( t r c ) aut o p r echarge be g i n dont c are figure 3. bankactivate command c y cle (burst length = n) 2 bank precharge command (ras# = "l", cas# = "h", we# = "l", bas = bank, a10 = "l", a0 - a9 and a11 = don't care) the bankprecharge command precharges the bank designated by ba si gnal. the precharged bank is switched from the active state to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in the desired bank. the maximum time any bank can be active is specified by t r as (max.). therefore, the precharge funct i on must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 precharge all command (ras# = "l", cas# = "h", we# = "l", bas = d ont care, a10 = "h", a0 - a9 and a11 = don't care) the prechargeall command precharges all banks simultaneously and can be issued even if all banks are not in the active state. all ba n ks are then switched to the idle state. 4 r ead command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "l", a0 - a7 = column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd ( min.) before the read command is issued. during read bursts, the valid data - out element from the starting column address will be available following the cas# latency after the issue of the read co mmand. each subsequent data - out element will be valid by the next positive clock edge (refer to the followi ng figure). the dqs go into high - impedance at the end of the burst unless other command is initiated. the burst length, bur st sequence, and cas# latency are determined by the mode register, which is alre ady programmed. a full - page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue. 6 rev2.0 may 2014
february 20 11 as 4 c 4m16s t0 t1 t2 t3 t4 t5 t6 t7 t8 c l k comma n d r e a d a nop nop nop nop nop nop nop n o p c a s# lat e ncy = 2 t c k2 , dq dout a 0 dout a 1 dout a 2 d ou t a 3 c a s# lat e ncy = 3 t c k3 , dq dout a 0 do u t a 1 d ou t a 2 d o u t a 3 figure 4. burst read operation (burst length = 4, cas# la tency = 2, 3) the read data appears on the dqs subject to the values on the dqm inputs two clocks earlier (i.e. dqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or writ e command to the same bank or the other active bank before the end of the burs t length. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the read command can occur on any clock cycle following a previous read command (refer to the following figure). clk t0 t1 t2 t3 t4 t5 t6 t7 t 8 comm a nd cas# latency=2 t ck2, dq cas# latency=3 t ck3, dq re a d a read b nop nop nop nop n o p n o p nop dout a 0 dout b 0 dout b 1 d o ut b 2 d o u t b 3 dout a 0 dout b 0 dout b 1 dout b 2 d o u t b 3 figure 5. read interrupted by a read (burst length = 4, cas# latency = 2, 3) the dqm inputs are used to avoid i/o contention o n the dq pins when the interrupt comes from a write command. the dqms must be asserted (high) at least two clocks prior to the write command to suppress data - out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with high - im pedance on the dq pins must occur between t he last read data and the write command (refer to the following three figures). if the data output of the burst read occurs at the second clock of the burst write, the dqms must be asserted (high) at least one clock prior to the write command to avoid internal bus contention. 7 rev2.0 may 2014
nop n o p february 20 11 as 4 c 4m16s clk t0 t1 t2 t3 t4 t5 t 6 t 7 t 8 t9 dqm comm a nd b a nka act i va t e nop nop r ead a wri t e a n o p n o p nop c a s # la t e nc y =2 t ck 2 , dq m ust b e hi - z bef o re the w rite command d i n a 0 di n a 1 d i n a 2 d i n a 3 figure 6. read to write interval (burst length 4, cas# latency = 2) c l k t0 t1 t2 t 3 t 4 t5 t6 t7 t8 dqm c o m ma nd n o p read a n o p nop nop nop w r ite b nop nop cas# l a tency=3 t ck3, dq dout a 0 d i n b 0 d i n b 1 d i n b 2 m u st be h i - z before the write command dont c are figure 7. read to write interval (burst length R 4, cas# latency = 3) c l k t0 t1 t 2 t3 t4 t 5 t6 t7 t8 d q m c o m ma nd nop nop r ead a nop nop wr ite b nop nop nop c a s # l atency=2 di n b 0 di n b 1 di n b 2 d i n b 3 t c k2, d q m ust be hi - z b ef o re the write comman d dont care figure 8. read to write interval (burst length 4, cas# latency = 2) a read burst without the auto precharge function m a y be interrupted by a bankprecharge/ precharge all command to the same bank. the following figure shows the opti mum time that bankprecharge/ precharge all command is issued in different cas# latency. 8 rev2.0 may 2014
february 20 11 as 4 c 4m16s clk t0 t1 t2 t3 t4 t5 t 6 t7 t 8 ad d ress comm a nd b a nk, c o l a read a nop nop n o p b a nk ( s) prech ar g e trp nop n o p b a nk r o w a c tiva t e n o p c a s # l a tency=2 t c k 2, dq c a s # l a tency=3 t c k 3, dq dout a 0 d o u t a 1 dout a 0 dout a 2 dout a 1 d o u t a 3 d o u t a 2 dout a 3 dont c are figure 9. read to precharge (cas# latency = 2, 3) 5 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "h", a0 - a7 = column address) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this command is given, a ny s ubsequent command cannot occur within a time delay of { t r p (min.) + burst length}. at full - page burst, only the read operation is performed in this command and the auto precharge function is ignored. 6 write command (ras# = "h", cas# = "l", we# = "l" , bas = bank, a10 = "l", a0 - a7 = column address) the write command is u sed to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. durin g write bursts, the first valid data - in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). the dqs remain with high - impedance at the end of the burst unless another command is initiated. the burst length and burst sequence are determined by the mode register, which is already programmed. a full - page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). clk t0 t1 t2 t3 t4 t 5 t6 t7 t8 comm a nd nop write a n o p nop nop nop nop n o p n op d q d i n a 0 d i n a 1 d i n a 2 di n a 3 dont care the first data element and the write a r e r e gis t er e d on t h e s ame c l o c k e d ge figure 10. burst write operation (burst length = 4) 9 rev2.0 may 2014
february 20 11 as 4 c 4m16s a write burst without the auto precharg e function may be interrupted by a subsequent write, bankprecharge/prechargeall, or read command before the end of the burst length. a n interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure). clk t 0 t1 t 2 t3 t4 t5 t6 t7 t8 comm a nd nop w r ite a write b nop n o p nop nop n o p n o p dq d i n a 0 d i n b 0 d i n b 1 di n b 2 di n b 3 figure 11. write interrupted by a write (burst length = 4) the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data - in element is regis tered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read command is registered, the data inputs will be igno red and writes will not be executed. clk t0 t1 t2 t3 t4 t5 t6 t7 t8 comm a nd n o p wr i te a read b nop n o p nop nop nop nop c a s # l a tency=2 t ck2, dq di n a 0 do n t c are dout b 0 dout b 1 dout b 2 dout b 3 c a s # l a tency=3 t ck3, dq di n a 0 do n t c are do n t c are dout b 0 dout b 1 dout b 2 dout b 3 input data must be removed from the dq at lea s t one clock cycle before the read data appears on t h e outputs to avoid data contention figure 12. write inte rrupted by a read (burst length = 4, cas# latency = 2, 3) the bankprecharge/prechargeall command that interrupts a write burst without t he auto precharge function should be issued m cycles after the clock edge in which the last data - in element is registe red, where m equals t w r / t c k rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, starting with the clock edge following the last data - in element an d ending with the clock edge on which the bankprecharge/prech argeall command is en t ered (refer to the following figure). 10 rev2.0 may 2014
february 20 11 as 4 c 4m16s clk t0 t1 t 2 t3 t4 t5 t6 t7 dqm c o m ma nd w r ite n o p nop trp p r e c h a r ge nop n o p a ct i v a t e nop a d dr e ss dq bank col n din n d i n n + 1 t wr b a n k ( s) r o w dont c are note: the ldqm/udqm can remain low in this example if the length of the write burst is 1 or 2. figure 13. write to precharge 7 write and autoprecharge command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "h", a0 - a7 = column address) the write and aut oprecharge command performs the precharge operation automatically after the write operation. once this command is given, any subsequent command cannot occur within a time delay of {(burst length - 1) + t w r + t r p (min.)}. at full - page burst, only t he write operation is performed in this command and the auto precharge function is ignored. clk t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 bank a w ri t e a b a nk a com m and activate nop nop auto p r ec h a rge n o p n o p nop nop t dal nop activate dq t dal =t wr +t rp di n a 0 di n a 1 beg i n a u top r e c ha r ge bank can be reactivated at completion of t d al figure 14. burst write w ith auto - precharge (burst length = 2) 8 mode register set command (ras# = "l", cas# = "l", we# = "l", a0 - a11 = register data) the mode register stores the data for controlling the various operating modes of sdram. the mode register set command programs the values of cas# latency, addressing mode and burst length in the mod e register to ma ke sdram useful for a variety of different applications. the default values of the mode register after power - up are undefined; therefore this command must be issued at the power - up sequence. the state of pins a0~a9 and a11 in the same cycle is the data wri tten to the mode register. two clock cycles are required to complete the write in the mode register (refer to the following figure). the contents of the mode register can be changed using the same command and the clock cycle requirements during operation a s long as all banks are in the idle state. 11 rev2.0 may 2014
a8 a7 test mode 0 0 normal 1 0 vend or use only 0 1 vendor use only a3 burst type 0 sequential 1 interleave a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 1 1 full page (sequential) all other reserved february 20 11 as 4 c 4m16s table 5. mode register bitmap ba0,1 a11,a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 rfu* rfu* wbl test mode cas# latency bt burst length a9 write burst length 0 burst 1 single bit a6 a5 a4 cas# latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 1 reserved all other reserved *note: rfu (reserved for future use) should stay 0 during mrs cycle. clk cke c s# t 0 t1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t9 t 1 0 t m rd ras# cas# we# ba 0 ,1 a10 a0 - a9, a11 addr e ss k e y dqm dq hi - z t rp prechargeall mo d e r e g i ster set comma n d any command dont c are figure 15. mode register set c y cle 12 rev2.0 may 2014
february 20 11 as 4 c 4m16s ? burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 2, 4, 8, or full page. table 6. burst length field a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page ? burst type field (a3) the burst type can be one of two modes, interleave mode or sequential mode. table 7. burst t y pe field a3 bur s t type 0 sequential 1 interleave ? burst d efinition, addressing sequen c e of sequential and interleave mode table 8. burst definition burst length start address sequential interleave a2 a1 a0 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page location = 0 - 255 n, n+1, n+2, n+3, 255, 0, 1, 2, n - 1, n, not support 13 rev2.0 may 2014
february 20 11 as 4 c 4m16s ? cas# latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first r ead data. the minimum whole value of cas# latency depends on the frequency of clk. the minimum whole value satisfying the following formula must be programmed into this field. t ca c (min) cas# latency x t ck table 9. cas# latency field a6 a5 a4 cas# laten c y 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "0 0" in normal operation. table 10. test mode field a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only ? write burst length (a9) this bit is used to select the write burst mode. when the a9 bit is "0", the burst - read - burst - write mode is selected. when the a9 bit is "1", the burst - read - single - write mode is selected. table 11. write burst length a9 write burst mode 0 burst - read - burst - write 1 burst - read - single - write note: a10 and ba0, 1 should stay l during mode set cycle. 9 n o - operation command (ras# = "h", cas# = "h", we# = "h") the no - operation command is used to perform a nop to the sdram which is selected (cs# is low). this prevents unwanted commands from being r egistered during idle or wait states. 10 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate eit her fixed - length or full - page bursts. this command is only effective in a read/write burst without the auto precharge func tion. the terminated read burst ends after a del ay equal to the cas# latency (refer to the following figure). the termination of a write burst is shown in the following figure. 14 rev2.0 may 2014
february 20 11 as 4 c 4m16s c l k t0 t1 t2 t3 t4 t 5 t6 t 7 t8 c o m ma nd re a d a nop nop n o p bu r st stop nop nop n o p nop c a s# late n cy=2 t h e burst en d s a f ter a delay equal t o the cas# latency t c k 2, dq c a s # l atency=3 t c k 3, dq dout a 0 dout a 1 d o ut a 2 d o u t a 0 dout a 1 dout a 3 dout a 2 dout a 3 figure 16 . termination of a burs t read operation ( bur s t l e ngth 4, c a s# latency = 2, 3) clk t0 t1 t2 t 3 t4 t5 t6 t7 t8 comm a nd dq nop w r ite a din a 0 nop din a 1 nop din a 2 b u rst stop nop n o p nop nop dont ca r e figure 17. termination of a burst write operati on (burst length = x) 11 device deselect command (cs# = "h") the device deselect command disables the command decoder so that the ras#, cas#, we# and address inputs are ignored, regardl e ss of whether the clk is enabled. t h is command is similar to the no operation command. 12 autorefresh command (ras# = "l", cas# = "l", we# = "h", c ke = "h", a11 = dont care, a0 - a9 = don't care) the autorefresh command is used during normal operation of the sdram and is analogous to cas# - before - ras# (cbr) refresh in con ventional drams. this command is non - persistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don't care" during an autorefresh command. the internal re fresh counter increments automatically on every auto refresh cycle to all of the rows. the refresh operation must be performed 4096 times within 64ms. the time required to complete the auto refresh operation is specified by t rc (min.). to provide the autore fresh command, a ll banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be followed by nops until the auto refresh operation is completed. the precharge time requirement, t r p (min), must be met before successive auto refresh operations are performed. 13 selfrefresh entry command (ras# = "l", cas# = "l", we# = "h", cke = "l", a0 - a9 = don't care) the selfrefresh is another refresh mode available in the sdram. it is the prefe rred refresh mode for data retention and low power opera t ion. once the selfrefresh command is registered, all the inputs to the sdram become "don't care" w ith the exception of cke, which must remain low. the refresh addressing and timing is internally gene rated to reduce power consumption. the sdram may remain in selfrefresh mode for an indefinite period. the selfref r esh mode is exited by res t arting the external clock and then asserting high on cke (selfrefresh exit command). 15 rev2.0 may 2014
february 20 11 as 4 c 4m16s 14 selfrefresh exit command this command is used to exit from the selfrefres h mode. once this command is registered, nop or device deselect commands must be issued for t x s r (min.) because time is required for the completion of any bank c urrently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be compl eted just prior to entering and just after exiting the selfrefresh mode. 15 clock suspend mode entry / powerdown mode entry command (cke = "l") when the sdram is operating the burst cycle, the internal clk is suspended (masked) from the subsequent cycle by issuing this command (asserting cke "low"). the device operation is held intact while clk is s uspended. on the other hand, when all ba n ks are in the idle state, this command performs entry into the powerdown mode. a ll input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspe nd or powerdown state longer than the refresh period (64ms) since the com m and does not perform any refresh operations. 16 clock suspend mode exit / powerdown mode exit command (cke= "h") when the internal clk has been suspended, the operation of the inter nal clk is reinitiated from the subsequent cycle by providing this command (asserting cke "high", the command should be nop or deselect). when the device is in the powerdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the powerdown mode. any subsequent commands can be issued after one clock cycle from the end of this command. 17 data write / output enable, data mask / output disable command (dqm = "l", "h") during a write cycle, the dqm signal functions as a data mas k and can control every word of the input data. during a read cycle, the dqm functions as the controller of output buffers. dqm is also used for device selection, byte selection and bus contr ol in a memory system. 16 rev2.0 may 2014
february 20 11 as 4 c 4m16s table 12. absolute maximum rating s y mbol item - 6/7 unit note v i n , v out input, output voltage - 1.0 ~ 4.6 v 1 v dd , v ddq power supply voltage - 1.0 ~ 4.6 v 1 t a ambient temperature 0 ~ 70 c 1 t stg storage temperature - 55 ~ 125 c 1 t solder soldering temperature (10 second) 260 c 1 p d power dissipation 1 w 1 i out short circuit output current 50 ma 1 table 13. recommended d.c. operating conditions ( t a = 0~70c) s y mbol parameter min. t y p. max. unit note v dd power supply voltage 3.0 3.3 3.6 v 2 v ddq power supply voltage(for i/o buffer) 3.0 3.3 3.6 v 2 v ih lvttl input high voltage 2.0 v dd q +0.3 v 2 v il lvttl input low voltage - 0.3 0.8 v 2 i i l input leakage current ( 0v v i n v dd , all other pins not under test = 0v ) - 10 10 a i ol output leakage current output disable, 0v v out v dd q ) - 10 10 a v oh lvttl output "h" level voltage ( i out = - 2ma ) 2.4 v v ol lvttl o utput "l" level voltage ( i out = 2ma ) 0.4 v table 14. capacitance (v d d = 3.3v, f = 1mhz, t a = 25c) s y mbol parameter min. max. unit c i input capacitance 2 5 pf c i/o input/output capacitance 4 6.5 pf note: these parameters are periodic a lly sampled and are not 100% tested. 17 rev2.0 may 2014
description/test condition s y mbol - 6 - 7 unit note max. operating current t r c t rc (min), outputs open one bank active i dd1 85 75 ma 3 precharge standby current in non - power down mode t c k = 15ns, cs# v i h (min), cke v ih input signals are changed every 2clks i dd2n 25 25 precharge standby current in non - power down mode t c k = , clk v i l (ma x ), cke v ih i dd2ns 15 15 precharge standby current in power down mode t c k = 15ns, cke v i l (ma x ) i dd2p 2 2 precharge standby current in power down mode t c k = , cke v i l (ma x ) i dd2ps 2 2 active standby current in non - power down mode t c k = 15ns, cke v i h (min), cs# v i h (min) input signals are changed every 2clks i dd3n 30 30 active standby current in non - power down mode cke v i h (min), clk v i l (ma x ), t c k = i dd3ns 25 25 operating current (burst mode) t ck = t c k (min), outpu ts open, multi - bank interleave i dd4 100 90 3, 4 refresh current t r c t rc (min) i dd5 130 120 3 self refresh current cke 0.2v ; for other inputs vi h R vdd - 0.2v, vil 0.2v i dd6 2 2 february 20 11 as 4 c 4m16s table 15. d.c. characteristics (v d d = 3.3v 0.3v, t a = 0~70c) 18 rev2.0 may 2014
february 20 11 as 4 c 4m16s table 16. electrical characteristics and recommended a.c. operating conditions (v d d = 3.3v 0.3v, t a = 0~70c) (note: 5, 6, 7, 8) s y m bol a.c. para m eter - 6 - 7 unit note min. max. min. max. t rc row c y cle time (same bank) 60 - 63 - ns t rcd ras# to cas# delay (same bank) 18 - 21 - t rp precharge to refresh/row activate command (same bank) 18 - 21 - t rrd row a c tivate to row a c tivate delay (different banks) 12 - 14 - t ras row activate to precharge time (same ba nk) 42 - 49 - t wr write reco v ery time 2 - 2 - t ck t ccd cas# to cas# delay time 1 - 1 - t ck clock c y cle t ime cl* = 2 10 - 10 - ns 9 cl* = 3 6 - 7 - t ch clock high time 2.5 - 2.5 - 10 t cl clock low time 2.5 - 2.5 - 10 t ac access time f r om clk (positive edge) cl* = 2 - 6 - 6 10 cl* = 3 - 5.4 - 5.4 t oh data output hold time 2.5 - 2.7 - 9 t lz data output low impedance 1 - 1 - t hz data output high impedance - 5 - 5.4 8 t is data/address/control input set - up time 1.5 - 1.5 - 10 t ih data/address/control input hold time 1 - 1 - 10 t pde power down e x it set - up time t is+ t ck - t is+ t ck - t mrd mode register set command cycle time 2 - 2 - t ck t refi refre s h interval time - 15.6 - 15.6 s t x sr exit self - refresh to read command t rc + t is - t rc + t is - ns * cl is cas# latency. note: 1. stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . vih (max) = 4.6v for pulse width Q 3ns. vil(min) = - 1.5v for pulse width Q 3ns. 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t c k and t rc . input signals are changed one time during every 2 t ck. 4. these paramet ers depend on the ou t put loading. specified values are obtained with the output open. 5. power - up sequence is described in note 11. 6. a.c. test conditions 19 rev2.0 may 2014
february 20 11 as 4 c 4m16s table 17. lvttl interface reference level of output sig nals 1.4v / 1.4v output load reference to the under output load (b) input signal levels 2.4v / 0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v 3.3v 1.4v 1 . 2 k ? 5 0 ? output 30pf 87 0 ? output z0=50 ? 30pf figure 18.1 lvttl d.c. test load (a) figure 18.2 lvttl a.c. test load (b) 7. transition times are measured between v i h and v i l . transition (rise and fall) of input signals are in a fixed slope (1 ns). 8. t h z defines the time in which the outputs achieve the open circuit condit i on and are not at reference levels. 9. if clock rising time is longer than 1 ns, ( t r / 2 - 0.5) ns should be added to the parameter. 10. assumed input rise and fall time t t ( t r & t f ) = 1 ns if t r or t f is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. power up sequence power up must be performed in the following seq uence. 1) power must be applied to v d d and v dd q (simultaneously) when cke= l, dqm= h and all input signals are held "nop" state . 2) start clock and maintain stable condition for minimum 200 s, then bring cke= h and, it is recommended that dqm is hel d "high" ( v d d levels) to ensure dq output is in high impedance. 3) all banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 2 auto - refresh dummy cycles must be required to stabilize the in ternal circuitry of the device. * the auto refresh command can be issue before or after mode register set command 20 rev2.0 may 2014
february 20 11 as 4 c 4m16s timing waveforms figure 19. ac parameters for write timing (burst length=4) clk t ch t 0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t1 1 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t cl cke c s# t is t is t ih begin auto pre c harge b ank a b e gin auto p r echarge bank b r a s# c a s# we# ba0,1 a 1 0 a 0 - a 9, t is t ih r a x r b x ray a 1 1 r a x c a x r b x c b x r a y c a y dqm dq h i - z t r c d t rc t d a l t is t ih t wr ax0 a x1 a x2 a x3 bx0 bx1 b x2 bx3 a y0 a y1 a y2 ay3 activate w r ite wi t h activate write with a c tivate w r ite precharge command auto pre c harge command auto p r echarge co m mand co m mand command bank a co m mand bank a bank b command bank b bank a bank a bank a d o nt care 21 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 20. ac parameters for read timing (burs t length=2, cas# latenc y = 2) clk cke t0 t1 t2 t3 t4 t5 t6 t7 t8 t ch t cl t is t9 t10 t1 1 t12 b e gin auto t13 t 1 4 t 1 5 t16 t ih cs# t is t ih p re c ha r g e bank b ras# ca s # we# ba 0 , 1 t ih a10 rax rbx ray a 0 - a 9 , a 1 1 dqm t is rax cax rbx t r r d t ras t ac t rc cbx ray dq h i - z t r cd t lz ax0 t oh t hz ax1 b x0 t rp bx1 t hz act i vate re a d activate read with precharge a c t i v a te command c o mmand c o mmand auto precharge command command ba n k a ba n k a ban k b command bank b ba n k a ban k a d o nt c a re 22 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 21. auto refresh (burst length=4, cas# latenc y = 2) clk t0 t 1 t2 t 3 t4 t5 t6 t7 t8 t9 t10 t11 t 12 t13 t14 t15 t16 t17 t 18 t19 t20 t21 t22 c k e cs# ras# cas# we# ba0 , 1 a10 r ax a0 - a9, a11 dqm t rp t rc t rc rax c a x t rcd dq p r e c h arge a ll c o m mand au t o refr e sh comma n d auto refr e s h command activate comma n d bank a r e ad command b a nk a a x0 a x1 dont care 23 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 22. po w er on sequence and auto refresh clk t0 t1 t 2 t 3 t4 t 5 t 6 t 7 t8 t9 t10 t11 t 12 t 1 3 t 14 t15 t16 t 17 t18 t19 t20 t21 t22 c ke cs# h igh l ev e l is r e gui r ed mi n i mum for 2 refresh cycles are requir e d r a s# c a s# we# ba0,1 a10 a0 - a9, a11 ad d r e s s key d qm dq h i - z t rp t mrd p r e c harge a l l command 1st auto ref r esh (*) comm a nd 2 n d auto refre s h ( *) co m mand any co m mand inputs mu s t be stable f or 200 s m o d e r eg is ter s e t command not e (*):the auto r e f r esh comm a nd can be is s u e be f ore or a fter mode re g ister set com m and d o nt care 24 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 23. self refresh entry & exit c y cle clk t 0 t 1 t2 t 3 t 4 t 5 t6 t 7 t 8 t 9 t 1 0 t11 t 12 t13 t 14 t15 t 16 t 1 7 t 18 t19 c k e c s # * n ote 1 t is * n ote 2 *n o te 3, 4 t x sr * n ote 5 t i s t ih * n ote 6 * n ote 7 * n ote 8 t p de r a s# c a s# * n ote 9 ba0,1 a0 - a 9, a11 w e # dqm d q h i - z h i - z self refresh entry self refresh exit a u t o refre s h d ont c are note: to enter selfrefresh mode 1. cs#, ras# & cas# with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock c an be don't care except for cke. 3. the device remains in selfrefre s h mode as long as cke stays "low". 4. once the device enters selfrefresh mode, minimum t ras is requ ired before exit from selfrefresh. to exit selfrefresh mode 5. system clock restart and be s t able before returning cke high. 6. enable cke and cke should be set high for valid setup time and hold time. 7. cs# starts from high. 8. minimum t x sr is requi red after cke going high to complete selfrefresh exit. 9. 4096 cycles of burst autorefresh is required before self refresh entry and after selfrefresh exit if the system uses burst refresh. 25 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 24.1. c lock suspension during burst read (using cke) (burst length=4, cas# latenc y = 2) c l k t 0 t1 t2 t3 t 4 t5 t6 t 7 t 8 t9 t10 t 11 t12 t 13 t 14 t 15 t16 t17 t 1 8 t 19 t 20 t 21 t 22 cke c s # ra s # ca s # we# b a 0,1 a10 a 0 - a9, a 11 rax rax cax d qm dq hi - z ax0 a x 1 a x 2 ax3 t hz ac ti va te c a m m a nd bank a r e ad com m and bank a cl o ck s u spend 1 cycle c lo c k susp e nd 2 cycles c lock sus p end 3 cycl e s dont care 26 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 24.2. clock suspension during burst read (using cke) (burst length=4, cas# latenc y = 3) clk t0 t1 t2 t3 t4 t5 t 6 t7 t8 t9 t10 t11 t12 t13 t14 t 1 5 t16 t17 t18 t19 t20 t21 t22 c k e cs# r a s # c a s# we# ba0,1 a 1 0 a0 - a 9, a11 rax rax cax dqm dq hi - z a x0 a x1 ax2 ax3 t hz acti v ate read cl o ck suspend clo c k suspend clock s uspend cam m and bank a command bank a 1 c ycle 2 c y cles 3 cy c les dont ca r e 27 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 25. clock suspension during burst write (using cke) (burst length=4) clk t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 1 0 t 1 1 t12 t13 t14 t15 t 16 t17 t 18 t19 t 20 t21 t22 c k e cs# ras# cas# we# ba0,1 a10 r a x a0 - a 9, a11 r ax c ax d q m dq hi - z d a x0 da x 1 d ax2 dax3 a ctivate c am m a n d bank a clock su s pe n d 1 cy c le write comma n d bank a clock su s pe n d 2 cy c les clock su s pend 3 cycl e s do nt care 28 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 26. po w er do w n mode and clock suspension (burst length=4, cas# latenc y = 2) clk t0 t 1 t2 t3 t4 t5 t 6 t 7 t 8 t 9 t 1 0 t 11 t12 t 1 3 t 14 t 15 t16 t17 t18 t 1 9 t 20 t 2 1 t 22 cke cs# t i h t is valid t p d e ras# cas# w e# ba0,1 a10 a0 - a9, a11 rax rax cax dqm dq hi - z active a x 0 ax1 ax2 t hz ax3 p rec h a r ge a c t i vate standby read cl o ck suspension clo ck suspe n s i o n p r ech a r ge s tandby p o wer down c a mm a nd ba n k a power down m o de entry com m and bank a pow e r down m o de e x it st a r t end com m and bank a power down m o de e ntry m o de e x it a n y com m ad dont care 29 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 27.1. random column read (page w ithin same bank) (burst length=4, cas# latenc y = 2) clk t 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t1 7 t 1 8 t 1 9 t 2 0 t2 1 t 2 2 c k e cs# ras# c a s# we# b a 0 , 1 a 1 0 r a w x r az a 0 - a 9, a 1 1 r aw caw cax c a y r az c a z dqm d q hi - z aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 az0 a c t i v a te c a mma n d b a nk a read c o mm a nd b a nk a r e ad comm a nd b a nk a read c o mm a nd b a n k a pr e char g e co m ma n d b a nk a a c t i v a te co m ma n d b a nk a read c o mm a nd b a n k a dont care 30 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 27.2. random column read (page w ithin same bank) (burst length=4, cas# latenc y = 3) clk t0 t 1 t2 t 3 t 4 t 5 t 6 t7 t8 t9 t 1 0 t1 1 t 1 2 t1 3 t 1 4 t 1 5 t1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 cke cs# r a s# c a s# we# ba 0 ,1 a10 r a wx r a z a0 - a 9, a11 r a w c aw c a x c a y r a z c az dqm dq hi - z a w 0 aw1 aw2 aw3 ax0 ax1 ay0 a y1 ay 2 ay3 a c t ivate read r e a d read precharge acti v a te read ca m mand com m a n d c o m m an d com m and com m and co m ma n d com m and ba nk a b a n k a ba n k a b a n k a b a n k a b a nk a b a n k a dont care 31 rev2.0 may 2014
february 20 11 as 4 c 4 m16s figure 28. random column write (page w ithin same bank) (burst length=4) c l k t 0 t1 t2 t 3 t 4 t 5 t6 t 7 t8 t 9 t 1 0 t1 1 t 1 2 t1 3 t1 4 t 1 5 t 1 6 t1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 c k e cs# r a s# c a s# we# b a 0 ,1 a10 rb w x rbz a 0 - a9, a 1 1 rbw cbw cbx cb y rbz cbz dqm d q hi - z db w0 db w 1 dbw 2 db w 3 d bx0 dbx1 db y 0 db y 1 d by2 dby3 db z 0 db z 1 ac t i v ate write write write prec h arge a c t i va te write ca m mand c o mm a nd c o mm a nd co m mand c o m m a nd c o m m a nd c o mm a nd bank b bank b bank b bank b b a n k b b a n k b bank b dont c are 32 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 29.1. random row r ead (interleaving banks) (burst length=8, cas# latenc y = 2) c lk t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 c k e h i gh cs# ras# cas# we# ba0,1 a10 rbx rax rby a0 - a 9, a11 rbx cbx rax cax rby cby d q m t rcd t ac t rp d q hi - z bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 a x1 ax2 a x 3 ax4 ax5 ax6 ax7 act i vate cammand bank b read command bank b a c tiv a te c o mmand ba n k a read command bank a p r e c ha r ge command bank b act i vate command bank b dont care read comm a nd ban k b 33 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 29.2. random row r ead (interleaving banks) (burst length=8, cas# latenc y = 3) clk t0 t1 t 2 t 3 t 4 t 5 t 6 t7 t 8 t 9 t10 t 1 1 t 12 t13 t 14 t 1 5 t 1 6 t17 t 18 t19 t 20 t21 t22 cke h i gh cs# ras# cas# we# b a 0,1 a10 rbx rax rby a0 - a9, rbx cbx rax cax rby cby a11 dqm t r c d t a c t rp d q hi - z bx0 b x1 bx2 bx3 bx4 b x5 b x6 b x7 ax0 ax1 ax2 ax3 a x4 ax5 ax6 ax7 by0 activate r e ad a c t ivate read p r echarge act i vate r e ad p recharge camma n d comma n d c o m mand com m and com m and co m mand comma n d c o m mand b a n k b bank b bank a bank a bank b bank b b a n k b bank a dont care 34 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 30. random row wri t e (interleaving banks) (burst length=8) clk t 0 t 1 t2 t 3 t4 t 5 t6 t 7 t8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t1 4 t 1 5 t 1 6 t 1 7 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 cke h i gh cs# ras# cas# w e # ba 0 ,1 a10 rax rbx ray a0 - a 9, a11 rax cax rbx cbx ray cay t r c d t w r * t rp t w r * dqm dq hi - z d a x0 d ax1 d ax2 da x 3 d ax4 d a x5 da x 6 d a x 7 d b x 0 db x 1 d b x 2 d b x 3 db x 4 d b x 5 db x 6 dbx7 d a y 0 da y 1 da y 2 day3 activate c a mm a nd b a nk a write co m m a n d b a nk a activate co m m and bank b write c o mm a nd b a nk b prech a rge c o mm a nd b a nk a a ctivate c om m a nd bank a write co m m and bank a prech a rge co m m a n d b a nk b * t wr > t wr ( m in.) d ont care 35 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 31.1. read and write c y cle (burst length=4, cas# latenc y = 2) c l k t0 t1 t 2 t3 t 4 t5 t6 t7 t 8 t9 t10 t 1 1 t 1 2 t13 t14 t 1 5 t 16 t 1 7 t 18 t 1 9 t 2 0 t 2 1 t 2 2 c ke c s# r as# c a s# w e # ba 0 ,1 a10 rax a 0 - a 9, a 1 1 rax cax cay c a z dqm dq hi - z a x 0 a x 1 a x 2 a x 3 da y 0 d ay 1 d a y3 a z 0 a z 1 a z3 activate re a d w rite the w rite d a ta re a d the r e a d d a ta c a m ma nd c o m ma nd c o mm a n d is masked with a c o m ma nd is masked with a ba n k a bank a bank a z e ro clo c k laten c y ba n k a two clock laten c y d o n t ca re 36 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 31.2. read and write c y cle (burst l ength=4, cas# latenc y = 3) clk t0 t1 t2 t 3 t 4 t 5 t 6 t7 t8 t9 t 1 0 t 1 1 t 12 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 18 t 1 9 t 20 t 2 1 t 2 2 cke c s# ras# c a s# we# ba 0 ,1 a 1 0 r ax a 0 - a 9 , a 1 1 r ax c ax c a y caz d qm dq h i - z a x 0 a x 1 a x 2 a x 3 day0 d a y1 d a y3 a z 0 a z1 az3 activate r e ad w rite the wri t e data the r e ad data ca m m a nd c o m m a nd c o m m a nd is m a sked w ith a is m a s k ed with a b a nk a b a nk a b a nk a zero clo c k l a t e ncy re a d c o m m and ba n k a two clo c k latency dont c are 37 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 32.1. interleaving column read c y cle (burst length=4, cas# latenc y = 2) clk t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t 2 1 t 2 2 cke c s # r a s# c a s# we# b a 0,1 a 10 r rax r b x a 0 - a 9, a 11 dqm rax cay t r cd t ac rbx cbw cbx cby cay cbz dq hi - z ax0 ax1 ax2 ax3 bw0 b w1 b x 0 bx1 by0 by 1 ay0 a y 1 bz0 bz1 bz2 bz3 activate read a c t i v a te re a d re a d r e a d r e a d r e a d precharge camm a nd comm a n d c o mma n d co m mand co m man d c o mma n d c o mma n d c o mma n d com m and ba n k a ba n k a ba nk b bank b bank b b a n k b ba nk a b a n k b pre c ha r g e c o mmand b ank a ba n k b dont c are 38 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 32.2. interleaved column read c y cle (burst length=4, cas# latenc y = 3) c l k t0 t 1 t2 t3 t 4 t5 t6 t7 t8 t 9 t 1 0 t11 t 1 2 t 13 t 1 4 t 1 5 t 16 t 1 7 t 1 8 t 1 9 t20 t 2 1 t 2 2 c k e c s # r a s# c as# we# b a 0 ,1 a 1 0 rax rbx a 0 - a9 , a 1 1 rax c a x rbx cbx cby c b z c ay dqm t r c d t ac d q hi - z a x 0 a x 1 a x 2 a x 3 bx0 bx1 by0 by1 bz0 b z 1 a y 0 a y 1 a y 2 a y 3 a c t i vate re a d re a d r e ad r e ad re a d pre c h a r g e precharge c a m ma n d c o m m and c o m m and c om m a nd c om m a nd c o m m and c o m m and c o m m a nd ba n k a b a nk a a c tivate c om m a nd bank b b a nk b bank b bank b b a nk a b a nk b bank a don t c a re 39 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 33. interleaved column write c y cle (burst length=4) clk t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 cke c s# r as# c a s# we# ba0,1 a10 rax rbw a0 - a9, a11 dqm rax t rcd cax r b w c bw cbx cby cay c b z t wr t wr d q h i - z t r r d >t rrd(min) d ax0 d ax1 d ax2 d ax3 d b w 0 d b w 1 d b x 0 d b x1 d b y0 d b y 1 d a y0 d a y1 d b z 0 d b z1 dbz2 dbz3 a c t i v a te write w r i te write write write write p re c h a rge c a m m a n d c o m m a n d command comman d command comman d command c o mmand b a n k a b a n k a a c t i v a te command b a nk b ba n k b b a nk b b a nk b b a n k a b an k b p r ec h a r ge command b a n k a b an k b don t care 40 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 34.1. auto precharge after read burst (burst length=4, cas# latenc y = 2) clk t0 t 1 t2 t3 t4 t5 t 6 t 7 t8 t9 t 1 0 t 1 1 t 1 2 t1 3 t 1 4 t1 5 t 1 6 t1 7 t 1 8 t1 9 t 2 0 t 2 1 t22 c ke hi g h b e gin auto prech a rge bank b b e g in a uto prech a rge b a nk a c s# ra s# c a s# we# ba 0 ,1 a 1 0 r a x rbx rby r a z a0 - a 9 , a11 d qm r ax c ax r bx cb x r ay t rp rby cby r a z dq hi - z a x 0 a x 1 a x 2 a x 3 b x 0 bx 1 b x 2 bx 3 ay 0 ay 1 a y 2 a y 3 b y 0 by 1 b y 2 activate c a mmand b a nk a r e ad c omm a nd bank a activate co m ma nd b a nk b r e a d w ith a uto p re c h a r g e c o mmand b a nk b re a d w ith a c tivate c ommand bank b r e a d w ith ac t iv a te c om m a nd bank a auto pr e ch a r g e c om m a nd bank a a uto pr e ch a r g e co m ma nd b a nk b don t c a re 41 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 34.2. auto precharge after read burst (burst length=4, cas# latenc y = 3) clk t0 t1 t 2 t3 t4 t5 t6 t7 t8 t9 t 1 0 t1 1 t 1 2 t 1 3 t 1 4 t1 5 t 1 6 t1 7 t 1 8 t 1 9 t 2 0 t 2 1 t22 cke hi g h c s # b e gin a u to precharge ba n k b b e gin a u to p r e c harge ba n k a ras# cas# we# ba 0 ,1 a 1 0 rax r b x r by a 0 - a 9, a 1 1 dqm r ax c ax r bx c bx c ay t rp r by c by dq h i - z ax 0 a x 1 ax 2 a x 3 b x 0 bx 1 b x 2 b x 3 ay 0 a y 1 a y 2 a y 3 b y 0 b y 1 b y2 activate cam m and ba n k a r e ad c ommand ba n k a activate co m m and ba n k b r e ad w i t h a u to p r e c h a r g e c ommand ba n k b read wi t h au t o p r e c ha r ge comma n d b a n k a ac t i va t e comma n d b a n k b read wi t h auto p r e c ha r ge comma n d b a n k b dont c are 42 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 34.1. auto precharge after read burst (burst length=4, cas# latenc y = 2) clk t0 t 1 t2 t3 t4 t5 t 6 t 7 t8 t9 t 1 0 t 1 1 t 1 2 t1 3 t 1 4 t1 5 t 1 6 t1 7 t 1 8 t1 9 t 2 0 t 2 1 t22 c ke hi g h b e gin auto prech a rge bank b b e g in a uto prech a rge b a nk a c s# ra s# c a s# we# ba 0 ,1 a 1 0 r a x rbx rby r a z a0 - a 9 , a11 d qm r ax c ax r bx cb x r ay t rp rby cby r a z dq hi - z a x 0 a x 1 a x 2 a x 3 b x 0 bx 1 b x 2 bx 3 ay 0 ay 1 a y 2 a y 3 b y 0 by 1 b y 2 activate c a mmand b a nk a r e ad c omm a nd bank a activate co m ma nd b a nk b r e a d w ith a uto p re c h a r g e c o mmand b a nk b re a d w ith a c tivate c ommand bank b r e a d w ith ac t iv a te c om m a nd bank a auto pr e ch a r g e c om m a nd bank a a uto pr e ch a r g e co m ma nd b a nk b don t c a re 43 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 36.1. full page read c y cle (burst length=full page, cas# latenc y = 2) clk t0 t1 t 2 t 3 t 4 t5 t 6 t 7 t 8 t 9 t 10 t 1 1 t 12 t 13 t 1 4 t 15 t 16 t 17 t 18 t19 t 20 t21 t 2 2 cke high cs# ras# cas# w e # b a 0,1 a 10 r a x rbx rby a 0 - a9, a 1 1 dqm dq r ax hi - z c ax rbx a x ax+1 ax+2 c b x r b y t rp a x - 2 ax - 1 a x ax+1 b x bx+1 b x +2 b x +3 bx+4 bx+5 bx+6 activ a te cam m and bank a read com m and bank a a c tivate c a mma n d b a nk b t he b u rst co u nter w raps fr o m the high e st or d er p age a d dress back t o zero d uring this t i me in t erval re a d c o mma n d b a nk b prec h arge co m mand ba n k b burst stop com m and a c tivate c o mma n d b a nk b f u ll pa g e bu r st op e ration does n ot te r mina t e when the b urst l ength is sat i sfied; t h e bu r st cou n ter i n creme n ts and cont i nues b ursti n g beg i nni n g with the s t arting addr e ss d o n t c a r e 44 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 34.1. auto precharge after read burst (burst length=4, cas# latenc y = 2) clk t0 t 1 t2 t3 t4 t5 t 6 t 7 t8 t9 t 1 0 t 1 1 t 1 2 t1 3 t 1 4 t1 5 t 1 6 t1 7 t 1 8 t1 9 t 2 0 t 2 1 t22 c ke hi g h b e gin auto prech a rge bank b b e g in a uto prech a rge b a nk a c s# ra s# c a s# we# ba 0 ,1 a 1 0 r a x rbx rby r a z a0 - a 9 , a11 d qm r ax c ax r bx cb x r ay t rp rby cby r a z dq hi - z a x 0 a x 1 a x 2 a x 3 b x 0 bx 1 b x 2 bx 3 ay 0 ay 1 a y 2 a y 3 b y 0 by 1 b y 2 activate c a mmand b a nk a r e ad c omm a nd bank a activate co m ma nd b a nk b r e a d w ith a uto p re c h a r g e c o mmand b a nk b re a d w ith a c tivate c ommand bank b r e a d w ith ac t iv a te c om m a nd bank a auto pr e ch a r g e c om m a nd bank a a uto pr e ch a r g e co m ma nd b a nk b don t c a re 45 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 37. full page write c y cle (burst length=full page) clk t0 t 1 t2 t 3 t4 t 5 t6 t 7 t8 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 t 1 7 t 1 8 t1 9 t 2 0 t 2 1 t 2 2 cke high c s # r a s# c as# w e# ba0 ,1 a10 r ax rbx rby a0 - a9, a11 rax cax r b x c bx rby dqm dq hi - z d a x da x + 1 da x + 2 da x +3 da x - 1 dax da x +1 dbx db x +1 d b x +2 db x +3 db x + 4 db x + 5 data is i g nored act i vate w r i te acti v a te w r ite pr e c har g e acti v a te cammand command camm a nd c o mm a nd c om m a nd command bank a bank a bank b the burst counter wraps from the hi g hest o r der bank b bank b burst stop c om m a nd b a n k b page address back to zero during th i s ti me i nterv a l full page burst o perati o n does not termina t e when the burst le n g th is satisfi e d; the burst counter increments and con t inues burst i ng beginn i ng w i th the starting address d o n t c a re 46 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 38. b y te write operation (burst length=4, cas# latenc y = 2) clk t0 t1 t 2 t 3 t4 t5 t6 t7 t8 t9 t10 t 11 t 12 t 1 3 t14 t 1 5 t16 t17 t18 t19 t20 t21 t 2 2 cke h i gh cs# ras# c a s# we# ba0,1 a 10 rax a0 - a 9, a11 rax cax cay caz dq m m dq m n d q0 - d q 7 a x 0 a x 1 a x 2 day 1 d a y2 a z 1 az2 d q8 - d q1 5 a x 1 a x 2 a x 3 day 0 day1 d a y 3 a z 0 a z 1 az2 a z 3 a c ti v a t e read u p p e r by te l o w e r b y t e wri t e u p p e r b y te r e ad l o w e r b y t e l o w er b y te c a m m a n d b a nk a c o mm a nd b a nk a is m a sked is m a sked c o m m a n d b a n k a i s m a s k ed c o m m a n d b a n k a is m a sked is ma s k ed dont c are 47 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 39. random row read (interleaving banks) ( burst length=4, cas# latenc y = 2) clk t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t 2 1 t22 cke h i gh b e gin a uto p r e c h a r ge b a n k b begin auto p re c harge bank a be g in auto p r e c h a rge bank b beg i n au t o p r e c ha r ge bank a cs# r a s# cas# we# b a 0 , 1 a10 rbu r a u rbv rav rbw a0 - a 9, a11 rb u cb u ra u ca u rbv cb v ra v ca v rbw d q m t rp t rp t rp d q bu0 bu1 bu 2 bu3 a u0 au1 a u2 a u3 b v 0 b v 1 bv2 bv3 a v 0 av1 av 2 a v 3 a c tiv a te c o mmand ba n k b ac t ivate command bank a re a d read ac t ivate command bank b read ac t ivate command bank a r e ad a c tiva t e c o m mand ba n k b bank b with a u to p r e c h arge bank a wi t h auto p r e c h arg e bank b with auto p r e c ha r ge ba n k a w i th auto p r echa r ge d o nt c a re 48 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 40. full page random column read (burst length=full page, cas# latenc y = 2) c l k t 0 t 1 t 2 t 3 t 4 t 5 t6 t7 t 8 t 9 t1 0 t1 1 t1 2 t1 3 t1 4 t1 5 t1 6 t 1 7 t 1 8 t 1 9 t 2 0 t2 1 t22 cke cs# r as # c a s# we# b a 0,1 a10 r a x rbx rbw a 0 - a 9 , a 1 1 d q m r a x t r r d rbx c a x t r c d cbx c a y cb y c az cb z rbw t rp d q hi - z a x 0 ax1 bx0 ay0 a y 1 b y 0 by1 az0 az1 az2 b z0 b z 1 b z 2 activa t e cam m and b a n k a activate com m and b a nk b read r e a d c o m m a n d b a n k b read r e a d c o m m a nd b a n k b read c o mm a nd bank a read c o mm a nd bank b p r e c ha r ge command bank b ( p r e cha r ge te m ina t ion) ac t i va t e com m a n d co m mand bank a com m and b a nk a b a n k b dont care 49 rev2.0 may 2014
february 20 11 as 4 c 4m16s figure 41. full page random column write (burst length=full page) clk t 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 0 t11 t12 t13 t 14 t15 t 1 6 t 1 7 t 18 t19 t 20 t21 t22 cke cs# ras# cas# we# ba0,1 a10 r ax rbx rbw a0 - a9, a11 r ax rbx cax cbx c a y cby caz cbz rbw dqm t rrd t rcd t wr t rp dq hi - z d a x 0 d a x1 db x0 d a y0 d a y1 d b y 0 db y1 d a z 0 d a z1 d a z2 d b z0 d b z1 d b z2 a c tivate activate write wr i te write write pr e char g e c a m m and co m m a nd co m m a n d c o m m and co m m a n d c om m a n d co m mand bank b ba n k a bank b bank b ba n k b bank a ba n k b (p r echar g e te m inatio n ) write c o m m an d ba n k a write c o m m and b a nk a write data a r e m a sked activate co m m a n d bank b figure 42. precharge termination of a burst (burst length=4, 8 or full page, cas# latenc y = 3) t0 t1 t2 t 3 t 4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t 16 t17 t 18 t 19 t20 t21 t22 clk c k e h igh c s # ras# cas# we# ba0,1 a10 r ax r a y r a z a 0 - a9, a 11 dqm r a x c a x t wr t rp ray cay r az t rp dq dax 0 da x 1 a y 0 a y 1 a y2 act i va t e c a m m a n d b a nk a w r ite c o mm a nd b a n k a p rec h a r ge c o m m a n d b a nk a a c tiv a te c o m m a nd b a n k a r e ad c o m m a nd b a n k a p re c h a rge c o mm an d b a nk a a c ti v ate c o m m a n d b a n k a pr e ch a rg e t er m in a t i o n p r echar g e terminat i o n of a wr i te b u r st wr i t e d a ta a r e m a sked 50 rev2.0 may 2014 of a read burst do n t care
febr uary 20 11 as 4 c 4m16s figure 43. 54 pin tsop ii package outline dra w ing information symbol dimension in inch dimension in mm min nom max min nom max a --- --- 0.047 --- --- 1.2 a1 0.002 --- 0.008 0.05 --- 0.2 a2 0.035 0.039 0.043 0.9 1.0 1.1 b 0.01 0.014 0.018 0.25 0.35 0.45 c 0.004 0.006 0.008 0.12 0.165 0.21 d 0.87 0.875 0.88 22.09 22.22 22.35 e 0.395 0.400 0.405 10.03 10.16 10.29 e --- 0.031 --- --- 0.8 --- he 0.455 0.463 0.471 11.56 11.76 11.96 l 0.016 0.02 0.024 0.4 0.5 0.6 l1 0.032 --- --- 0.84 --- s --- 0.028 --- --- 0.71 --- y --- --- 0.004 --- --- 0.1 0 --- 8 0 --- 8 notes: 1. dimension d&e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. dimension s includes end flash. 4. controlling dimension: mm 51 rev2.0 may 2014
4m4 february 20 11 as 4 c 4m16s orde ring inform a tion alliance organization vc c range package operating temp speed mhz as4c4m16 s - 6tc n 4m x 16 3.3v+/ - 0.3v 54 tsop ii commercial 166 as4c4m16 s - 6ti n 4m x 16 3.3v+/ - 0.3v 54 tsop ii industrial 166 as4c4m16 s - 7tcn 4m x 16 3.3v+ / - 0.3v 54 tsop ii commercial 143 part numbering system as4c 4m16s - 6 t=tsop package c n sdram prefix s= sdram 64mb (4mx16) speed 54 pin tsop ii temperature range c = commercial (0 - 70c) i = industrial ( - 45 - 85c) n = lead fr ee r ohs compliant part 52 rev2.0 may 2014

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